Optimizing FPGA Design

This application note describes how EnFuzion was used to control the execution of the NeoCAD Place-and-Route utility on a multi-FPGA-based circuit. EnFuzion allowed developers to experiment with a number of design parameters, enhancing their design.

What is the NeoCad FPGA Foundry?
The NeoCad FPGA Foundry is a complete high performance set of back-end tools for the design and implementation of Field Programmable Gate Arrays (FPGA), targeted at the Xilinx FPGA Family. It contains the following components:

  • Technology mapping
  • Interactive graphical editing for programmable ICs (EPIC)
  • Automatic placement and routing (PAR)
  • Partitioning (PRISM)
  • Timing Analysis

How did EnFuzion help with the design process?
The designers used EnFuzion to control the execution of the NeoCAD Place-and-Route utility on a multi-FPGA-based circuit. EnFuzion allowed the designers to experiment with a number of design parameters and to explore different design options for a high performance computer architecture for solving combinatorial optimization problems using simulated annealing. See Guess for more details.

How was EnFuzion used in the development of NeoCAD FPGA Foundry?
The designers explored two main parameters:

  • The cycle time of the machine
  • The choice of cost table for the routing software

In this application, 50 jobs were run across four workstations. The total execution time was 48 hours and 46 minutes (taking 12 hours and 50 minutes on the four workstations.) This represents almost perfect speedup.

The following plan file was used to control the experiment:

parameter period label "Clock Period (nsecs)"
    integer select anyof 50 75 100 125 150 175 default 100;
parameter table label "Cost Table" integer range from 1 to 10 step 1;
task nodestart
    copy tsp_fpga0.ncd node:.
    copy tsp_fpga0.prf.skel node:.
task main
    node:substitute tsp_fpga0.prf.skel tsp_fpga0.prf
    node:execute par -w -l 3 -t $table -u 1 tsp_fpga0.ncd \
        tsp_fpga0_r.ncd tsp_fpga0.prf
    copy node:tsp_fpga0* output.$jobname

The nodestart task copies the NeoCad design file (*.ncd) and the parameter file to the node. The parameter file (tsp_fpga0.prf.skel) contains design parameters, including a placeholder for the clock period.

The main task substitutes the placeholder for clock period and runs the Place-and-Route utility. Note that the cost table parameter ($table) is passed on the command line. At the end of the run, the files are copied back to the root and stored in a unique directory.

The output files have been post-processed using a number of awk scripts. The results of the run are shown in the following Excel chart. Here it is clear that the machine is incapable of running at 75 nsecs. The minimum design score occurs with cost table 9 on the 100 nsec design.



In another experiment, the designers compared the performance of the 100 nsecs design across all 100 cost tables. The results are shown here:



The following screen shows the best of the designs; it depicts the distribution of the circuit across the FPGA.



Further information
This application note describes some basic capabilities of EnFuzion. It uses EnFuzion 6.0 release. You can find out more about using EnFuzion from the user manual or on the Axceleon Web site at www.axceleon.com.

Copyright © 2002 Axceleon Inc. All Rights Reserved